In computer systems, it is required to drive relatively large on-chip loads, such as for example, a long interconnect. On-chip interconnects, such as, for example, buses and bitlines, are found in virtually all components making up a computer system. Consider the computer system illustrated in FIG. 1. In FIG. 1, die 102 comprises a microprocessor with many sub-blocks, such as arithmetic logic unit (ALU) 104 and on-die cache 106. Die 102 may also communicate to other levels of cache, such as off-die cache 108. Higher memory hierarchy levels, such as system memory 110, are accessed via host bus 112 and chipset 114. In addition, other functional units not on die 102, such as graphics accelerator 116 and network interface controller (NIC) 118, to name just a few, may communicate with die 102 via appropriate buses or ports. Each of these functional units may physically reside on one die or more than one dice. Some or parts of more than one functional unit may reside on the same die. Each of these various described components requires driving large loads, such as long interconnects. As clock frequencies for the various chips and buses in a computer system increase, high-speed signaling by heavily loaded drivers presents challenges.
Full-swing, on-chip signal signaling schemes may generally be considered as either dynamic or static. A dynamic signaling scheme may be abstracted in FIG. 2a, where a dynamic driver comprising pFET (Field-Effect-Transistor) 202, nFET 204, and nFET 206 either charges or discharges interconnect 208 to HIGH (Vcc) or LOW (Vss). Interconnect 208 may be a long interconnect or a large load, for example. A clock signal is provided to the gates of pFET 202 and nFET 206. Data is provided to the gate of nFET 204. During a pre-charge phase, the clock signal is LOW so that pFET 202 charges interconnect (load) 208 HIGH. During an evaluation phase, the clock signal is HIGH so that pFET 202 switches OFF, and interconnect 208 is conditionally discharged LOW depending upon the data signal provided to the gate of nFET 204.
Although dynamic signaling schemes are usually relatively fast, they may consume a considerable amount of power even when the data activity is zero (e.g., when the data signal is HIGH over a number of clock cycles). This is due to the power dissipated in clocking the pre-charge devices, as well as the unnecessary full-swing transitions on the interconnects.
In static schemes, drivers, repeaters, and receivers are typically simple CMOS static gates, such as inverters. A static scheme may be abstracted in FIG. 2b, where driver 210 and receiver 212 are static inverters. Interconnect 214 may be a large interconnect or large load, for example. Unlike a dynamic scheme, there is no significant power consumption for zero data activity. Furthermore, there is no clocked device that leads to clock power dissipation. However, in contrast to a dynamic scheme, both rising and falling signals received at the input of receiver 212 should be evaluated equally fast. Consequently, it has been desirable in static schemes that receivers should be symmetrical with an inversion threshold in the middle of the power rails. That is, denoting the HIGH and LOW power rail voltages as Vcc and Vss, respectively, the inversion threshold has historically been set at (Vcc−Vss)/2. But for signals with slow edge rates, there may be an undesirable delay before a signal reaches the inversion threshold for a symmetrical receiver. This may result in considerable delay and degrade the performance of a bus.
A fast, asymmetrical static receiver has been proposed in Tomofumi Iima, et al., “Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI,” IEEE Journal of Solid State Circuits, Vol. 31., no. 4, April 1996, pp 531–536, and is shown in FIG. 2c. However, there are some disadvantages to the circuit of FIG. 2c. This will be addressed after describing the proposed embodiments.